Referring to FIG. 1, a power semiconductor device according to the prior art includes a plurality of spaced gate trenches 3, each having a gate insulation 5 body (typically composed of silicon dioxide) lining the sidewalls thereof, and a gate electrode 7 disposed therein. Gate trenches 3 in a prior art device have terminal ends 9. In a known design, a gate bus 11 (which has been rendered transparent for better illustration) is disposed over at least one end 9 of each gate trench 3 in electrical contact with a gate electrode 7 therein.
It is a common commercial practice to rate a power semiconductor device prior to shipping the same to an end user. To perform a voltage breakdown rating, the device is subjected to, for example, a certain screening voltage.
It has been observed that gate insulation 5 at end 9 has been a source of premature breakdown. Therefore, screening voltages have been set low to avoid the premature breakdown during rating and qualification. As a result, it has been difficult to isolate devices with trench defects and the like during the screening and qualification process.
It is, therefore, desirable to reduce or eliminate premature gate insulation breakdown in order to improve the rating and qualification process.
In U.S. application Ser. No. 11/338,215, filed Jan. 24, 2006 and assigned to the assignee of the present application, a power semiconductor device is disclosed which overcomes the problems discussed above. FIGS. 2 and 3 illustrate the device disclosed in U.S. application Ser. No. 11/338,215.
Referring to FIGS. 2 and 3, a power semiconductor device 6 includes drift region 10 of a first conductivity (e.g. N-type), base region 12 of a second conductivity (e.g. P-type) over drift region 10, a plurality of endless trenches 14 extending through base region 12 to drift region 10, a gate insulation layer 16 formed in each endless trench 14 adjacent at least base region 12, and an endless gate electrode 18 residing in each endless trench 14. Each endless trench 14 includes two spaced parallel trenches 14′, and two opposing connecting trenches 14″ connecting parallel trenches 14′.
Device 6 further includes conductive regions 22 of the first conductivity over body region 12 adjacent each parallel trench 14′ of each endless trench 14. Furthermore, a high conductivity region 24 of the second conductivity type but of lower resistivity than body region 12 (e.g. P+) is formed in body region 12 between two opposing conductive regions 22.
Conductive regions 22 are part of what is commonly referred to as an active region. As seen in the FIGS. 2 and 3, each endless trench 14 is spaced from another endless trench 14 by an active region, and includes an active region within an interior region 15 thereof. Furthermore, connecting trenches 14″ are curved.
Gate bus 20 (which has been rendered partially transparent for better illustration) is disposed over at least a portion of one connecting trench 14″ of each endless trench 14 and electrically connected to gate electrode 18 disposed therein. Furthermore, each endless trench 14 has a curved bottom, and thick insulation body 26 (thicker than gate insulation 16) over the curved bottom. Drift region 10 is an epitaxially formed semiconductor body residing over a substrate 28 of the same semiconductor material and the same conductivity.
Device 6 further includes first power electrode 30 ohmically connected to conductive regions 22 and high conductivity regions 24, and second power electrode 32 electrically connected to substrate 28.